8.2. PSCI Performance Measurements on Arm Juno Development Platform
This document summarises the findings of performance measurements of key operations in the Trusted Firmware-A Power State Coordination Interface (PSCI) implementation, using the in-built Performance Measurement Framework (PMF) and runtime instrumentation timestamps.
8.2.1. Method
We used the Juno R1 platform for these tests, which has 4 x Cortex-A53 and 2 x Cortex-A57 clusters running at the following frequencies:
Domain |
Frequency (MHz) |
|---|---|
Cortex-A57 |
900 (nominal) |
Cortex-A53 |
650 (underdrive) |
AXI subsystem |
533 |
Juno supports CPU, cluster and system power down states, corresponding to power levels 0, 1 and 2 respectively. It does not support any retention states.
Given that runtime instrumentation using PMF is invasive, there is a small (unquantified) overhead on the results. PMF uses the generic counter for timestamps, which runs at 50MHz on Juno.
The following source trees and binaries were used:
Please see the Runtime Instrumentation Testing Methodology page for more details. The tests were ran using the tf-psci-lava-instr/juno-enable-runtime-instr,juno-instrumentation:juno-tftf configuration in CI.
8.2.2. Results
8.2.2.1. CPU_SUSPEND to deepest power level
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
332440.0 |
270640.0(+1031.44%) |
169500.0(+22.05%) |
0 |
1 |
624520.0(-1.01%) |
30260.0(-88.07%) |
166740.0(+21.76%) |
1 |
0 |
187960.0(+1.74%) |
25460.0(+9.93%) |
90420.0(+12.69%) |
1 |
1 |
479100.0 |
20520.0(+10.56%) |
87500.0(+14.38%) |
1 |
2 |
923480.0(-1.11%) |
294160.0(+1.58%) |
87500.0(+14.62%) |
1 |
3 |
1106300.0 |
238320.0 |
87340.0(+14.35%) |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
333000.0(-52.92%) |
23920.0(-40.11%) |
138880.0(-17.24%) |
0 |
1 |
630900.0(+145.95%) |
253720.0(-46.56%) |
136940.0(+1987.50%) |
1 |
0 |
184740.0(+71.92%) |
23160.0(-95.39%) |
80240.0(+1283.45%) |
1 |
1 |
481140.0(+18.16%) |
18560.0(-88.25%) |
76500.0(+1520.76%) |
1 |
2 |
933880.0(+67.76%) |
289580.0(+189.64%) |
76340.0(+1510.55%) |
1 |
3 |
1112480.0(+9.76%) |
238420.0(+753.94%) |
76380.0(-15.32%) |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
267000.0(+9.39%) |
31080.0(+26.96%) |
168520.0(+22.44%) |
0 |
1 |
267440.0(+9.52%) |
30680.0(+28.69%) |
168480.0(+22.21%) |
1 |
0 |
291300.0(-1.18%) |
25140.0(+6.80%) |
86980.0(+13.52%) |
1 |
1 |
184260.0(+2.31%) |
23140.0(+9.46%) |
87940.0(+14.03%) |
1 |
2 |
184520.0(+2.20%) |
23460.0(+12.79%) |
87520.0(+14.02%) |
1 |
3 |
184700.0(+2.27%) |
23240.0(+9.62%) |
87180.0(+13.43%) |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
244080.0(-9.21%) |
24480.0(-40.00%) |
137640.0(-18.19%) |
0 |
1 |
244200.0(-9.06%) |
23840.0(-41.57%) |
137860.0(-17.91%) |
1 |
0 |
294780.0(-1.56%) |
23540.0(-14.83%) |
76620.0(-12.35%) |
1 |
1 |
180100.0(+74.72%) |
21140.0(-6.63%) |
77120.0(+1533.90%) |
1 |
2 |
180540.0(+75.25%) |
20800.0(-10.34%) |
76760.0(+1554.31%) |
1 |
3 |
180600.0(+75.44%) |
21200.0(-7.99%) |
76860.0(+1542.31%) |
8.2.2.2. CPU_SUSPEND to power level 0
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
683780.0(-2.74%) |
22560.0(+33.81%) |
11040.0(+38.35%) |
0 |
1 |
829620.0(-2.61%) |
22820.0(+39.15%) |
11480.0(+42.79%) |
1 |
0 |
104520.0(-74.34%) |
17200.0(+13.91%) |
8680.0(+20.56%) |
1 |
1 |
249200.0(+124.54%) |
17100.0(+10.61%) |
8480.0(+29.27%) |
1 |
2 |
393980.0(-28.95%) |
17480.0(+13.51%) |
8320.0(+19.88%) |
1 |
3 |
539520.0(+108.34%) |
16980.0(+9.13%) |
8300.0(+25.00%) |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
703060.0(-17.69%) |
16860.0(-47.87%) |
7980.0(-19.88%) |
0 |
1 |
851880.0(+20.98%) |
16400.0(-49.41%) |
8040.0(-17.45%) |
1 |
0 |
407400.0(+58.99%) |
15100.0(-26.20%) |
7200.0(-5.76%) |
1 |
1 |
110980.0(-72.67%) |
15460.0(-23.47%) |
6560.0(-10.87%) |
1 |
2 |
554540.0 |
15400.0(-23.46%) |
6940.0(-2.53%) |
1 |
3 |
258960.0(+143.06%) |
15560.0(-25.05%) |
6640.0 |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
101100.0(-4.73%) |
22820.0(+33.45%) |
7360.0(+39.92%) |
0 |
1 |
101400.0(-5.13%) |
22720.0(+33.18%) |
7560.0(+43.18%) |
1 |
0 |
291440.0 |
16880.0(+8.21%) |
4580.0 |
1 |
1 |
96600.0(-6.45%) |
16860.0(+9.20%) |
4600.0(+3.14%) |
1 |
2 |
97060.0(-6.40%) |
16980.0(+11.27%) |
4640.0(+3.11%) |
1 |
3 |
96660.0(-6.77%) |
16960.0(+7.89%) |
4620.0(+2.67%) |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
106120.0(+1.49%) |
17100.0(-48.24%) |
5260.0(-23.77%) |
0 |
1 |
106880.0(+2.40%) |
17060.0(-47.08%) |
5280.0(-21.89%) |
1 |
0 |
294360.0 |
15600.0(-20.97%) |
4560.0 |
1 |
1 |
103260.0(+3.82%) |
15440.0(-20.41%) |
4460.0(-5.11%) |
1 |
2 |
103700.0(+4.33%) |
15260.0(-24.08%) |
4500.0(-2.60%) |
1 |
3 |
103680.0(+4.26%) |
15720.0(-20.53%) |
4500.0(-1.32%) |
8.2.2.3. CPU_OFF on all non-lead CPUs
CPU_OFF on all non-lead CPUs in sequence then, CPU_SUSPEND on the lead
core to the deepest power level.
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
267240.0(+9.97%) |
32940.0(+24.68%) |
168460.0(+22.45%) |
0 |
1 |
267340.0(+9.46%) |
33720.0(+28.12%) |
168500.0(+22.21%) |
1 |
0 |
185740.0(+1.85%) |
25120.0(+6.17%) |
88380.0(+13.31%) |
1 |
1 |
101940.0(-5.77%) |
24240.0(+6.88%) |
4600.0(+4.07%) |
1 |
2 |
101800.0(-6.04%) |
23060.0(+6.17%) |
4660.0(+9.91%) |
1 |
3 |
101820.0(-5.91%) |
23340.0(+7.66%) |
4640.0(+6.91%) |
Cluster |
Core |
Powerdown |
Wakeup |
Cache Flush |
0 |
0 |
243020.0(-9.14%) |
26420.0(-39.51%) |
137580.0(-17.85%) |
0 |
1 |
244240.0(-8.87%) |
26320.0(-38.93%) |
137880.0(-17.73%) |
1 |
0 |
182360.0(-2.89%) |
23660.0(-15.20%) |
78000.0(-11.08%) |
1 |
1 |
108180.0(+4.68%) |
22680.0(-14.16%) |
4420.0 |
1 |
2 |
108340.0(+4.92%) |
21720.0(-16.40%) |
4240.0(-4.93%) |
1 |
3 |
108220.0(+4.82%) |
21680.0(-16.16%) |
4340.0(-3.12%) |
8.2.2.4. CPU_VERSION in parallel
Cluster |
Core |
Latency |
0 |
0 |
1200.0(+20.00%) |
0 |
1 |
1160.0(+9.43%) |
1 |
0 |
700.0(+16.67%) |
1 |
1 |
1040.0(+4.00%) |
1 |
2 |
1020.0(+4.08%) |
1 |
3 |
1080.0(+8.00%) |
Cluster |
Core |
Latency |
0 |
0 |
1000.0(-19.35%) |
0 |
1 |
1060.0(-17.19%) |
1 |
0 |
600.0(-11.76%) |
1 |
1 |
1000.0(+2.04%) |
1 |
2 |
980.0(+4.26%) |
1 |
3 |
1000.0(+2.04%) |
8.2.3. Annotated Historic Results
The following results are based on the upstream TF master as of 31/01/2017. TF-A was built using the same build instructions as detailed in the procedure above.
In the results below, CPUs 0-3 refer to CPUs in the little cluster (A53) and CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead CPU.
PSCI_ENTRY corresponds to the powerdown latency, PSCI_EXIT the wakeup latency, and
CFLUSH_OVERHEAD the latency of the cache flush operation.
8.2.3.1. CPU_SUSPEND to deepest power level on all CPUs in parallel
CPU |
|
|
|
|---|---|---|---|
0 |
27 |
20 |
5 |
1 |
114 |
86 |
5 |
2 |
202 |
58 |
5 |
3 |
375 |
29 |
94 |
4 |
20 |
22 |
6 |
5 |
290 |
18 |
206 |
A large variance in PSCI_ENTRY and PSCI_EXIT times across CPUs is
observed due to TF PSCI lock contention. In the worst case, CPU 3 has to wait
for the 3 other CPUs in the cluster (0-2) to complete PSCI_ENTRY and release
the lock before proceeding.
The CFLUSH_OVERHEAD times for CPUs 3 and 5 are higher because they are the
last CPUs in their respective clusters to power down, therefore both the L1 and
L2 caches are flushed.
The CFLUSH_OVERHEAD time for CPU 5 is a lot larger than that for CPU 3
because the L2 cache size for the big cluster is lot larger (2MB) compared to
the little cluster (1MB).
8.2.3.2. CPU_SUSPEND to power level 0 on all CPUs in parallel
CPU |
|
|
|
|---|---|---|---|
0 |
116 |
14 |
8 |
1 |
204 |
14 |
8 |
2 |
287 |
13 |
8 |
3 |
376 |
13 |
9 |
4 |
29 |
15 |
7 |
5 |
21 |
15 |
8 |
There is no lock contention in TF generic code at power level 0 but the large
variance in PSCI_ENTRY times across CPUs is due to lock contention in Juno
platform code. The platform lock is used to mediate access to a single SCP
communication channel. This is compounded by the SCP firmware waiting for each
AP CPU to enter WFI before making the channel available to other CPUs, which
effectively serializes the SCP power down commands from all CPUs.
On platforms with a more efficient CPU power down mechanism, it should be
possible to make the PSCI_ENTRY times smaller and consistent.
The PSCI_EXIT times are consistent across all CPUs because TF does not
require locks at power level 0.
The CFLUSH_OVERHEAD times for all CPUs are small and consistent since only
the cache associated with power level 0 is flushed (L1).
8.2.3.3. CPU_SUSPEND to deepest power level on all CPUs in sequence
CPU |
|
|
|
|---|---|---|---|
0 |
114 |
20 |
94 |
1 |
114 |
20 |
94 |
2 |
114 |
20 |
94 |
3 |
114 |
20 |
94 |
4 |
195 |
22 |
180 |
5 |
21 |
17 |
6 |
The CFLUSH_OVERHEAD times for lead CPU 4 and all CPUs in the non-lead cluster
are large because all other CPUs in the cluster are powered down during the
test. The CPU_SUSPEND call powers down to the cluster level, requiring a
flush of both L1 and L2 caches.
The CFLUSH_OVERHEAD time for CPU 4 is a lot larger than those for the little
CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
to the little cluster (1MB).
The PSCI_ENTRY and CFLUSH_OVERHEAD times for CPU 5 are low because lead
CPU 4 continues to run while CPU 5 is suspended. Hence CPU 5 only powers down to
level 0, which only requires L1 cache flush.
8.2.3.4. CPU_SUSPEND to power level 0 on all CPUs in sequence
CPU |
|
|
|
|---|---|---|---|
0 |
22 |
14 |
5 |
1 |
22 |
14 |
5 |
2 |
21 |
14 |
5 |
3 |
22 |
14 |
5 |
4 |
17 |
14 |
6 |
5 |
18 |
15 |
6 |
Here the times are small and consistent since there is no contention and it is only necessary to flush the cache to power level 0 (L1). This is the best case scenario.
The PSCI_ENTRY times for CPUs in the big cluster are slightly smaller than
for the CPUs in little cluster due to greater CPU performance.
The PSCI_EXIT times are generally lower than in the last test because the
cluster remains powered on throughout the test and there is less code to execute
on power on (for example, no need to enter CCI coherency)
8.2.3.5. CPU_OFF on all non-lead CPUs in sequence then CPU_SUSPEND on lead CPU to deepest power level
The test sequence here is as follows:
Call
CPU_ONandCPU_OFFon each non-lead CPU in sequence.Program wake up timer and suspend the lead CPU to the deepest power level.
Call
CPU_ONon non-lead CPU to get the timestamps from each CPU.
CPU |
|
|
|
|---|---|---|---|
0 |
110 |
28 |
93 |
1 |
110 |
28 |
93 |
2 |
110 |
28 |
93 |
3 |
111 |
28 |
93 |
4 |
195 |
22 |
181 |
5 |
20 |
23 |
6 |
The CFLUSH_OVERHEAD times for all little CPUs are large because all other
CPUs in that cluster are powerered down during the test. The CPU_OFF call
powers down to the cluster level, requiring a flush of both L1 and L2 caches.
The PSCI_ENTRY and CFLUSH_OVERHEAD times for CPU 5 are small because
lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
an L1 cache flush.
The CFLUSH_OVERHEAD time for CPU 4 is a lot larger than those for the little
CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
to the little cluster (1MB).
The PSCI_EXIT times for CPUs in the big cluster are slightly smaller than
for CPUs in the little cluster due to greater CPU performance. These times
generally are greater than the PSCI_EXIT times in the CPU_SUSPEND tests
because there is more code to execute in the “on finisher” compared to the
“suspend finisher” (for example, GIC redistributor register programming).
8.2.3.6. PSCI_VERSION on all CPUs in parallel
Since very little code is associated with PSCI_VERSION, this test
approximates the round trip latency for handling a fast SMC at EL3 in TF.
CPU |
TOTAL TIME (ns) |
|---|---|
0 |
3020 |
1 |
2940 |
2 |
2980 |
3 |
3060 |
4 |
520 |
5 |
720 |
The times for the big CPUs are less than the little CPUs due to greater CPU performance.
We suspect the time for lead CPU 4 is shorter than CPU 5 due to subtle cache effects, given that these measurements are at the nano-second level.
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