7.27. NXP S32G274A

S32G2 is an NXP vehicle network processor combining ASIL D safety, hardware security, high-performance real-time and application processing and network acceleration. S32G2 supports the needs of new vehicle architectures: service-oriented gateways, domain controllers, zonal processors, safety processors and more. It is equipped with 4 Cortex-A53 cores operating at 1.0GHz.

The TF-A includes support for one single S32G2-based board called S32G274ARDB2. The S32G-VNP-RDB2 is a compact, highly optimized and integrated board engineering for vehicle service-oriented gateway (SoG), domain control applications, high-performance processing, safety and security applications. More details about this board can be found at s32g274ardb2.

7.27.1. Boot Flow

BootROM -> BL2 (SRAM) -> BL31 (DDR) -> BL33 (DDR)

Warning

This boot flow is a preliminary version that will serve as a foundation for upcoming S32G2 contributions.

7.27.2. Code Locations

  • Downstream TF-A: link:

  • Downstream U-Boot: link

  • Downstream Linux: link

7.27.3. How to build

The port currently available on the S32G274ARDB2 platform is in its initial stage. The boot process takes advantage of both SRAM and DDR memory. BootROM loads BL2 into SRAM, and BL2 is responsible for initializing DDR and loading subsequent stages (such as BL31 and BL33) into their designated memory regions. To create a bootable image, the script below should be used. This script makes use of the mkimage tool, which is part of the U-Boot drop for S32G274A SoCs.

Warning

The DDR_FW_BIN_PATH parameter must point to the location of the folder containing the DDR firmware binary specific to the S32G274ARDB2 platform. This binary is essential for proper DDR initialization. It is included in the Linux BSP releases for the S32G274A-RDB board and can be obtained from https://www.nxp.com/.

#!/bin/bash -xe
TF_A="${TF_A:-`pwd`}"
UBOOT="${UBOOT:-${TF_A}/../u-boot}"
DDR_FW="${DDR_FW:-${TF-A}/../ddr-firmware}"
DEBUG="${DEBUG:-1}"

FIP_BASE="0x34100000"

if [ "${DEBUG}" -eq "1" ]; then
        BUILD="debug"
else
        BUILD="release"
fi

BOOT_IMAGE="build/s32g274ardb2/${BUILD}/BOOT_IMAGE.bin"
BL2_BIN="build/s32g274ardb2/${BUILD}/bl2.bin"
FIP_BIN="build/s32g274ardb2/${BUILD}/fip.bin"

# Generate bl2, bl31 and fip image
make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \
        BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" clean DDR_FW_BIN_PATH="${DDR_FW}/ddr_fw_ecc_off.bin"
make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \
        BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" bl2 DDR_FW_BIN_PATH="${DDR_FW}/ddr_fw_ecc_off.bin"
make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \
        BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" fip DDR_FW_BIN_PATH="${DDR_FW}/ddr_fw_ecc_off.bin"

# Extract BL2 entry
BL2_START="0x$(poetry run memory -p s32g274ardb2 -b debug footprint | \
                        grep BL2 | awk -F'|' '{print $3}' | xargs)"
# BL2 bin file size in bytes
BL2_SIZE="$(stat -c "%s" "${BL2_BIN}")"

# Pack bl2.bin and fip.bin by ensuring that the FIP image will start at FIP_BASE
cp -vf "${BL2_BIN}" "${BOOT_IMAGE}"
dd if="${FIP_BIN}" of="${BOOT_IMAGE}" seek="$((FIP_BASE - BL2_START))" bs=1

# Build a bootable image by appending the IVT
"${UBOOT}/tools/mkimage" \
        -a "${BL2_START}" \
        -e "${BL2_START}" \
        -T s32ccimage \
        -n "${UBOOT}/u-boot-s32.cfgout" \
        -d "${BOOT_IMAGE}" \
        fip.s32

7.27.4. SoC Errata Workarounds

The S32G274A port of the TF-A includes compilation flags that can be used to control the workaround for the SoC. These flags are used similarly to how the CPU Errata Workarounds are used. The list of workarounds includes the following switches:

  • ERRATA_S32_051700: This applies erratum ERR051700 workaround to SoCs part of the S32 Common Chassis family, and therefore it needs to be enabled for the S32G and S32R devices.