7.12. Intel Agilex72 SoCFPGA

Agilex72 SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A720/A520 processor.

Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes the hardware, then loads bl31 and bl33 (Linux/Baremetal/Zephyr/FreeRTOS) into DDR and boots to bl33.

Boot ROM --> Trusted Firmware-A --> BL33

7.12.1. How to build

7.12.1.1. Code Locations

Trusted Firmware-A: link

7.12.1.2. Build Procedure

Fetch all the above 2 repositories into local host. Make all the repositories in the same ${BUILD_PATH}.
Prepare the AARCH64 toolchain.

make CROSS_COMPILE=aarch64-linux-gnu- device=agx72

make CROSS_COMPILE=aarch64-linux-gnu- bl2 bl31 fip PLAT=agilex72

7.12.1.3. Install Procedure

dd fip.bin to a A2 partition on the MMC drive to be booted in Agilex72 board.
Generate a SOF containing bl2

aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0x00000000 bl2.bin bl2.hex
quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2>

Configure SOF to board

nios2-configure-sof <output_sof_with_bl2>

7.12.2. Boot trace

INFO:    DDR: DRAM calibration success.
INFO:    ECC is disabled.
NOTICE:  BL2: v2.15(debug)
NOTICE:  BL2: Built
INFO:    BL2: Doing platform setup
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0x00000000
INFO:    SPSR = 0x3cd
NOTICE:  BL31: v2.15(debug)
NOTICE:  BL31: Built
INFO:    ARM GICv2 driver initialized
INFO:    BL31: Initializing runtime services
WARNING: BL31: cortex_a520
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x50000
INFO:    SPSR = 0x3c9